The present invention relates to electronic circuits, and more particularly, to charge pump circuits.
The performance of a phase-locked loop (PLL) is generally characterized by the timing of the feedback clock signal with respect to the timing of the reference clock signal. When a PLL is in lock mode, the average time difference between the phase of the reference clock signal and the phase of the feedback clock signal at the inputs of the phase-frequency detector (PFD) is referred to as the static phase error (SPE).
FIG. 1A illustrates a prior art charge pump circuit 100 used in a PLL. Charge pump circuit 100 includes p-channel metal oxide semiconductor field-effect transistors (MOSFETs) 101-102, n-channel MOSFETs 103-104, unity gain amplifier 105, and two variable current sources 106 and 107.
A phase-frequency detector (not shown) generates four digital control signals UP, UPb, DN, and DNb. UPb is the digital inverse of UP, and DNb is the digital inverse of DN. The UP signal controls the conductive state of p-channel MOSFET 101. The UPb signal controls the conductive state of p-channel MOSFET 102. The DNb signal controls the conductive state of n-channel MOSFET 103. The DN signal controls the conductive state of n-channel MOSFET 104.
Variable current source 106 contains a MOSFET that generates a current IUP, and variable current source 107 contains a MOSFET that generates a current IDN. The current settings for IUP and IDN are achieved by varying the gate-source voltages of the MOSFETs in current sources 106 and 107, which changes the voltage headroom requirement. Larger current settings for current sources 106 and 107 require more voltage headroom. When the drain-source voltages of the MOSFETs in currents sources 106 and 107 are not sufficient to cause the MOSFETs to be in saturation, currents IUP and IDN may be mismatched. The mismatch of IUP and IDN is one of the sources of SPE in the PLL. Therefore, the single-transistor implementation of current source 106 and current source 107 is not optimum to handle different charge pump current settings.
FIG. 1B illustrates a prior art charge pump circuit used in a PLL. Charge pump circuit 150 in FIG. 1B includes MOSFETs 101-104, unity gain amplifier 105, current sources 111-114 and 121-124, and switches SU1, SU2, SUn, SD1, SD2, and SDn. Current sources 111-114 generate currents IUP1, IUP2, IUP3, and IUPn, respectively. Current sources 121-124 generate currents IDN1, IDN2, IDN3, and IDNn, respectively. One or more of switches SU1, SU2, SUn, etc. and corresponding switches SD1, SD2, SDn, etc. are opened or closed to vary the current through charge pump 150.
The gate-source voltages of the MOSFETs in current sources 111-114 and 121-124 are constant and independent of the total current through charge pump 150. The voltage headroom requirement is also fixed, and charge pump 150 generates less SPE.